On High-Quality, Low Energy BIST Preparation at RT-Level

The purpose of this paper is to discuss how a recently proposed RT (Register Transfer) Level test preparation methodology can be reused to drive innovative LowEnergy (LE) / Low-Power (LP) BIST solutions for digital SOC (System on a Chip) embedded cores. RTL test generation is carried out through the definition of a reduced set of masks, forcing few "care" bits, and leading to a high correlation between multiple detection of RTL faults and single detection of likely physical defects. LE/LP BIST sessions are defined as short test sequences leading to high values of RT-level IFMB metrics and low-level Defects Coverage (DC). The Weighted Switching Activity (WSA) of the BIST sessions, with and without mask forcing, is computed. It is shown that, by forcing vectors with the RTL masks, short BIST sessions, with low energy and with a comparable (or smaller) average power consumption, as compared to pseudo-random test, are derived. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and modules of the CMUDSP and TORCH ITC'99 benchmark circuits.